A CMOS Programmable Analog Memory-Cell Array Using Floating-Gate Circuits

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells. I. DEFINITION OF AN E-POT MODERN analog, neuromorphic, or mixed-mode VLSI chips typically have large numbers of inputs and analog parameters, and the number of available pins is often a limiting factor in these systems. Often, these parameters and other biases are stored off-chip as voltages programmed by potentiometers or other sources, one pin per variable (see Fig. 1). Pins are also needed for inputs and outputs. The number of pins available on a chip is limited by the perimeter of the chip, which grows as the square root of die area. If we could move the analog parameters and circuit biases onto the chip, we would save more pins for input, output, and diagnostics (see Fig. 1). Also, storing biases on-chip could significantly reduce circuit board complexity. If we think of potentiometers as easily modifiable voltage sources, then we would like to build an electronic version of the pot, an e-pot, that can be placed on the chip itself. If large numbers of these cells can be placed on one chip, then they will supply more biases than could the few pins required to program them. We have the following requirements for our e-pot. 1) Nonvolatile: An e-pot must maintain its state indefinitely in the absence of power. Manuscript received April 2000; revised November 2000. This work was supported by the Center for Neuromorphic Systems Engineering under the National Science Foundation’s Engineering Research Center Program. The work of R. R. Harrison was supported by DARPA and NIMH under grants. This paper was recommended by Associate Editor T. S. Lande. R. R. Harrison is with the Electrical Engineering Department, University of Utah, Salt Lake City, UT 84112 USA (e-mail: [email protected]). J. A. Bragg, P. Hasler, and S. P. Deweerth are with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA (e-mail: [email protected]). B. A. Minch is with the School of Electrical Engineering, Cornell University, Ithaca, NY 14853 USA. Publisher Item Identifier S 1057-7130(01)02012-2. Fig. 1. Using electronic potentiometers (e-pots). (a) On typical analog VLSI chips, many of the pins are consumed by bias voltages set with off-chip potentiometers. (b) By storing these voltages on-chip, many pins are freed for I/O. 2) Small: We would like to get reasonable numbers of these devices on one chip in order to have many “virtual pins.” 3) Few Pins: Because our goal is to save pins, a large array of e-pots should require few pins for I/O and biases. 4) Wide Voltage Range: An e-pot should be able to store any voltage from ground to the power-supply rail. 5) “Tweakable”: We must be able to move an e-pot’s voltage up or down smoothly, just like turning the knob on a potentiometer. 6) Individually Addressable: We must have control over each e-pot, like an array of real potentiometers (i.e., no global erase necessary). 7) Flexible Supply Voltage: The e-pot array should function using a wide range of supply voltages and only require additional voltage sources during the programming process. 1057–7130/01$10.00 © 2001 IEEE HARRISON et al.: CMOS PROGRAMMABLE ANALOG MEMORY-CELL ARRAY 5 Fig. 2. E-pot circuit schematic. (a) Single e-pot cell. The floating gate is connected to the negative input of an amplifier with feedback capacitor C . This pins the floating-gate voltage to V and allows V to be moved from rail to rail by changing the charge of the floating gateQ . Charge is removed from the floating gate through tunneling. The tunneling voltage is switched with a high-voltage differential amplifier built with lightly doped-drain nFETs. The capacitive coupling of the tunneling voltage to the floating gate is counterbalanced by switching a lower voltage V on a larger capacitor. Charge is added to the floating gate through hot-electron injection. Gate 2 is a pseudo-pMOS NAND gate; we use these symbols for clarity. The high-voltage amplifier is shown in Fig. 5. The amplifier is a ten-transistor nFET-input wide-output-range transconductance amplifier [10]. (b) Array of e-pots with shift register used for addressing. The tunnel, inject, and select lines carry digital signals. 8) High Programming Precision: More precision is always desirable. Recent advances in floating-gate CMOS circuits open up the possibility for building on-chip nonvolatile e-pots [1]–[6]. In this paper, we describe a floating-gate CMOS e-pot array that meets the requirements listed above. We have described preliminary testing of these structures in [2]. An earlier floating-gate memory cell was built by Diorio et al.[5]. Our e-pot design has many advantages over this design. By using a high-gain differential amplifier in a feedback configuration, we have explicit control of the floating-gate voltage. In addition, the output amplifier has nFET inputs, preventing any leakage resulting from pFET hot-electron injection. Our memory cells are configured as an addressable array with no crosstalk, and high-voltage switches in each e-pot make a global erase unnecessary. Programming has been further simplified by cancelling the capacitive coupling inherent in tunneling, allowing the output voltage to be monitored during the programming process. Finally, our cells can be designed to use either an nFET-injector or a pFET-injector structure, allowing fabrication in standard CMOS processes. II. CIRCUIT DESCRIPTION The circuit schematic is shown in Fig. 2. We designed and fabricated arrays of e-pots in commercially available 2.0m BiCMOS and 1.2m and 0.8m CMOS processes. We configured the e-pot circuits in a one-dimensional (1-D) array along the edge of each 2.2 mm 2.2 mm chip. Addressing circuitry was included in the arrays [see Fig. 2(b)]. In the 2.0m process, each e-pot measures 69 m 333 m, allowing 23 elements to be placed in the array. The 1.2m process reduced the element size to 41.4 m 231.6 m, allowing us to place 39 elements in the array. An e-pot array of arbitrary length consumes 11 pins for control signals and other biases. Once programming is completed, the array needs only three off-chip biases. In order to make the e-pots nonvolatile, we use floating-gate MOS transistors [1]. A floating gate is a polysilicon node surrounded by SiO , trapping charge on the gate indefinitely. The floating gate is connected to the negative input of a high-gain amplifier with a feedback capacitor . This effectively pins the floating-gate voltage at , the positive input to the amplifier. A. Controlling the Array The e-pot elements are arranged in a 1-D array, with only one of those elements being “active” at a given time. It is important to note that e-pots are still sourcing voltage into the chip when they are not active. The first control signal is a clock that advances the shift register depicted in Fig. 2(b), causing the next e-pot in the array to become active. The pin presents the output voltage of the active e-pot, while the sync output presents the logic high signal when, after stepping through the entire array, the shift register rolls over and the first e-pot becomes active again. The tunnel and inject input signals control charge flow onto and off of the floating node, which in turn controls the output voltage of the amplifier. Tunneling, by removing electrons from the floating gate, increases the floating-gate voltage and reduces the output voltage. Injection, by placing electrons onto the floating gate, reduces the floating-gate voltage and increases the output voltage. Fig. 3 shows a typical tunnel/inject cycle for an e-pot fabricated in a 2.0m BiCMOS process; e-pots fabricated in the 1.2m standard CMOS process performed similarly. While programming individual e-pots, we measured no crosstalk to other e-pots due to tunneling or injection in either of the two processes. Fig. 4 illustrates the independent control available over the individual e-pots; in this example, the pots have been programmed in a cosine pattern. We have set e-pots to voltages from 10 mV above ground to the power-supply rail. 6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 1, JANUARY 2001 Fig. 3. Experimental measurement illustrating e-pot operation. Digital signals control tunneling and hot-electron injection, moving the e-pot output voltage up or down smoothly. B. Electron Tunneling and Capacitive Compensation To decrease an e-pot’s output voltage, we remove electrons from its floating gate by the process of Fowler–Nordheim tunneling [9]. This process uses a high-voltage source to create an energy barrier thin enough that electrons can tunnel through the gate oxide; typical tunneling voltages used are 35–40 V in 2.0m processes and 27–30 V in 1.2m processes (based on other measurements, we expect tunneling voltages in the range of 10–12 V in 0.5m processes). We switch high voltages on-chip with a high-voltage differential amplifier built with lightly doped-drain nFETs, which use well diffusion as their drain regions (see Fig. 5). The resulting high-voltage nFETs have breakdown voltages greater than 45 V. In the CMOS process we use, it is not possible to create high-voltage pFETs, so we simply let the pFETs in the diffamp break down. This happens at a of 20 V, so our high-voltage diffamp cannot completely “turn off.” The output varies between around 40V in the “on” mode to around 15 V in the “off” mode. However, the tunneling current depends exponentially on the reciprocal of the oxide voltage, so at V, there is no observable tunneling current. It should be noted that after the e-pots are programmed, the tunneling voltage can be removed and there is no further need for a high-voltage source. By switching the tunneling and injection voltages locally, we achieve individually programmable memory cells, with no need